1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, a liquid crystal display device and a fabricating method thereof with double metal layer source and drain electrodes.
2. Description of the Background Art
Generally, a liquid crystal display (LCD) controls light transmittance using an electric field to display a picture. To this end, the LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal panel. The liquid crystal panel is provided with pixel electrodes for applying an electric field to each liquid crystal cell, and a common electrode. Typically, the pixel electrode is provided on a lower substrate for each liquid crystal cell, whereas the common electrode is integrally formed on the entire surface of an upper substrate. Each of the pixel electrodes is connected to a thin film transistor (TFT) used as a switching device. The pixel electrode drives the liquid crystal cell, along with the common electrode, in accordance with a data signal applied via the TFT.
FIGS. 1 and 2 depict an LCD of the conventional art. As shown, a lower substrate 1 of the LCD includes a TFT T arranged at an intersection between a data line 13 and a gate line 11, a pixel electrode 23 connected to a drain electrode 7 of the TFT, and a storage capacitor S positioned at an overlapping portion between the pixel electrode 23 and the pre-stage gate line 11.
The TFT T includes a gate electrode 3 connected to the gate line 11, a source electrode 5 connected to the data line 13, and a drain electrode 7 connected, via a drain contact hole 19a, to the pixel electrode 23. Further, the TFT T includes semiconductor layers 15 and 17 for defining a channel between the source electrode 5 and the drain electrode 7 by a gate voltage applied to the gate electrode 3. Such a TFT T responds to a gate signal from the gate line 11 to selectively apply a data signal from the data line 13 to the pixel electrode 23.
The pixel electrode 23 is positioned at a cell area divided by the data line 13 and the gate line 11 and is made from a transparent conductive material having a high light transmittance. The pixel electrode 23 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) by a data signal applied via the drain contact hole 19a. By this potential difference, a liquid crystal positioned between the lower substrate 1 and the upper substrate (not shown) is rotated due to its dielectric anisotropy. Thus, the liquid crystal allows a light applied, via the pixel electrode 23, from a light source to be transmitted into the upper substrate.
The storage capacitor S charges a voltage in an application period of a gate high voltage to the pre-stage gate line 11 while discharging the charged voltage in an application period of a data signal to the pixel electrode 23. This prevents a voltage variation in the pixel electrode 23. The storage capacitor S includes a gate line 11 and a storage electrode 25. The storage electrode 25 overlaps the gate line 11, and a gate insulating film 9 is positioned between the storage electrode 25 and the gate line 11. Further, the storage capacitors is electrically connected to the pixel electrode 23 via a storage contact hole 19b defined by a protective film 21.
Hereinafter, a conventional method of fabricating the lower substrate 1 of the LCD having the above-mentioned configuration will be described. The conventional method is depicted in FIGS. 3A–3E.
First, a gate metal layer is deposited onto the lower substrate 1 and patterned to form the gate line 11 and the gate electrode 3, as shown in FIG. 3A. An insulating material is entirely deposited onto the lower substrate 1 in such a manner to cover the gate line 11 and the gate electrode 3. The insulating material forms the gate insulating film 9 shown in FIG. 3B. First and second semiconductor materials are sequentially deposited onto the gate insulating film 9 and then patterned to form an active layer 15 and an ohmic contact layer 17.
Subsequently, as shown in FIG. 3C, a data metal layer is deposited onto the gate insulating film 9 and patterned to form the storage electrode 25, the source electrode 5 and the drain electrode 7. Thereafter, as shown in FIG. 3D, a protective film 21 is formed on the gate insulating film 9, The protective film 21 is then patterned to define the drain contact hole 19a and the storage contact hole 19b in such a manner to expose the drain electrode 7 and the storage electrode 25.
Subsequently, as shown in FIG. 3E, a transparent conductive material is deposited onto the protective film 21 and patterned to form the pixel electrode 23 such that the pixel electrode electrically contacts the drain electrode 7 and the storage electrode 25.
The source electrode 5 and the drain electrode 7 provided on the lower substrate 1 of such a LCD device are formed from a data metal layer such as chrome (Cr) or molybdenum (Mo) in a single layer structure.
FIGS. 4A–4B depict another conventional LCD device which trends towards a relatively higher resolution than the conventional LCD device of FIGS. 1 and 2. As shown, when the device trends toward a relatively higher resolution, the data metal layer has a double layer structure of first and second metal layers 6a and 6b. The first metal layer 6a is made from a metal such as molybdenum (Mo) or titanium (Ti) while the second metal layer 6b is made from a material such as aluminum (Al) or an aluminum alloy.
When the data metal layer having the double layer structure is patterned by the wet etching, it may be over-etched by a certain area D1 in comparison to a photo resist pattern 27. When this occurs, if the ohmic contact layer 17 at a portion corresponding to the gate electrode 3 is patterned by the wet etching with the aid of the photo resist pattern 27, the active layer 15 is exposed as shown in FIG. 4B. This creates a parasitic capacitance Cgd between the gate metal layer, and the data metal layer has a deviation equal to about D2 due to the over-etched data metal layer, which results in increased difficulty in obtaining uniform picture quality.